The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for analyzing and debugging circuitry within an integrated circuit.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been an increase in difficulty of the processes used for manufacturing the devices.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual circuits are functional, it is also important to ensure that batches of circuits perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Several testing techniques have been developed for integrated circuits for detecting failure modes such as gate-oxide shorts, bridging defects, parasitic transistor leakage, defective p-n junctions, and transistors with incorrect threshold voltages. Such faults may pass functional and logical testing, but can malfunction over time, causing reliability problems. Many of those faults cause elevated quiescent power supply current (Iddq), which is typically several orders of magnitude greater than the Iddq of a fault-free device. For example, in static random-access memories (SRAMs), most of the Iddq testable faults are activated during the write/read cycles. By monitoring an output current level, Iddq testing has been shown as an effective way for testing integrated circuits such as CMOS combinational circuits, and can also be effective for detecting SRAM defects that escape traditional voltage monitoring techniques. In typical Iddq testing, the device under test (DUT) has a constant voltage power supply and the current is monitored for changes. These changes are used to analyze the DUT. One problem associated with Iddq testing is the difficulty of measuring the Iddq current. In particular, obtaining an accurate current measurement from a DUT exhibiting high current can be difficult, inefficient, and produce inaccurate results.
The present invention is directed to integrated circuit analysis, and is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, an integrated circuit device (DUT) is analyzed using a constant current source and a voltage detection device. The current source is electrically coupled to the DUT and the voltage is monitored while the current supply is held constant. Detected variations in voltage between test vectors at different clock cycles are used for evaluating the potential for a defect at the particular logic state associated with the clock cycle exhibiting a variation. By using a constant current source and monitoring the voltage, the difficulties associated with current measurement addressed hereinabove can be avoided. In this manner, the logic states having a defect can be isolated for additional testing, improving failure analysis of the DUT.